pa10 ? pa10a pa10u 1 pa10, pa10a 3 4 5 6 2 1 7 8 a1 d1 q1 q4 q3 q5 c1 q2a q2b q6b q6a typical application figure 1. voltage-to-current conversion dc and low distortion ac current waveforms are delivered to a grounded load by using matched resistors (a and b sections) and taking advantage of the high common mode rejection of the pa10. foldover current limit is used to modify current limits based on output voltage. when load resistance drops to 0, the current is limited based on output voltage. when load resistance drops to 0, the current limit is 0.79a resulting in an internal dissipa - tion of 33.3 w. when output voltage increases to 36v, the current limit is 1.69a. refer to application note 9 on foldover limiting for details. external connections s r r2b .82 .82 C42v +42v r2a r1a pa10 r1b load 0-24 control features ? g ain b andwid th product 4mhz ? t emperature range C55 to +125c (pa10a) ? e xcellent linearity class a/b output ? wide supply range 10v to 50v ? high output current 5a peak applications ? m otor, valve and actuator control ? m agnetic deflection circuits up to 4a ? po wer transducers up to 100khz ? t emperature control up to 180w ? programmable po wer supplies up to 90v ? a udio amplifiers up to 60w rms description the pa10 and pa10a are high voltage, high output current operational amplifers designed to drive resistive, inductive and capacitive loads. for optimum linearity, the output stage is biased for class a/b operation. the safe operating area (soa) can be observed for all operating conditions by selec - tion of user programmable current limiting resistors. both amplifers are internally compensated for all gain settings. for continuous operation under load, a heatsink of proper rating is recommended. this hybrid integrated circuit utilizes thick flm (cermet) resistors, ceramic capacitors and semiconductor chips to maximize reliability, minimize size and give top performance. ultrasonically bonded aluminum wires provide reliable inter - connections at all operating temperatures. the 8-pin to-3 package is hermetically sealed and electrically isolated. the use of compressible isolation washers voids the warranty. equivalent sc h ematic cl+ +v +in Cin Cv fo clC out s s top view r cl+ r clC output 1 2 3 4 5 6 7 8 power operational amplifier pa10 ? pa10a p r o d u c t i n n o v a t i o n f r o m 8-pin to-3 package style ce copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com may 2009 apex ? pa10urevr p r o d u c t i n n o v a t i o n f r o m
pa10 ? pa10a 2 pa10u specifications ab solute maximum ratings supply voltage, +v s to Cv s 100v output current, within soa 5a power dissipation, internal 67w input voltage, differential 37v input voltage, common mode v s temperature, pin solder - 10s 300c temperature, junction 1 200c temperature range, storage C65 to +150c operating temperature range, case C55 to +125c pa10 pa10a parameter test conditions 2, 5 min typ max min typ max units input offset voltage, initial t c = 25c 2 6 1 4 mv offset voltage, vs. temperature full temperature range 10 65 * 40 v/c offset voltage, vs. supply t c = 25c 30 200 * * v/v offset voltage, vs. power t c = 25c 20 * vw bias current, initial t c = 25c 12 30 10 20 na bias current, vs. temperature full temperature range 50 500 * * pa/c bias current, vs. supply t c = 25c .10 * pa/v offset current, initial t c = 25c 12 30 5 10 na offset current, vs. temperature full temperature range 50 * pa/c input impedance, dc t c = 25c 200 * m input capacitance t c = 25c 3 * pf common mode voltage range 3 full temperature range v s C5 v s C3 * * v common mode rejection, dc 3 full temp. range, v cm = v s C6v 74 100 * * db gain open loop gain at 10hz t c = 25c, 1k load 110 * db open loop gain at 10hz full temp. range, 15 load 96 108 * * db gain bandwidth product @ 1mhz t c = 25c, 15 load 4 * mhz power bandwidth t c = 25c, 15 load 10 15 * * khz phase margin full temp. range, 15 load 35 * output voltage swing 3 t c = 25c, i o = 5a v s C8 v s C5 v s C6 * v voltage swing 3 full temp. range, i o = 2a v s C6 * v voltage swing 3 full temp. range, i o = 80ma v s C5 * v current, peak t c = 25c 5 * a settling time to .1% t c = 25c, 2v step 2 * s slew rate t c = 25c 2 3 * * v/s capacitive load full temperature range, a v = 1 .68 * nf capacitive load full temperature range, a v = 2.5 10 * nf capacitive load full temperature range, a v > 10 soa * nf power supply voltage full temperature range 10 40 45 * * 50 v current, quiescent t c = 25c 8 15 30 * * * ma thermal resistance, ac, junction to case 4 t c = C55 to +125c, f > 60hz 1.9 2.1 * * c/w resistance, dc, junction to case t c = C55 to +125c 2.4 2.6 * * c/w resistance, junction to air t c = C55 to +125c 30 * c/w temperature range, case meets full range specifcations C25 +85 C55 +125 c the internal substrate contains beryllia (beo). do not break the seal. if accidentally broken, do not crush, machine, or subject to temperatures in excess of 850c to avoid generating toxic fumes. caution notes: * the specifcation of pa10a is identical to the specifcation for pa10 in applicable column to the left. 1. long term operation at the maximum junction temperature will result in reduced product life. derate internal power dissipation to achieve high mttf. 2. the power supply voltage for all tests is 40, unless otherwise noted as a test condition. 3. +v s and Cv s denote the positive and negative supply rail respectively. total v s is measured from +v s to Cv s . 4. rating applies if the output current alternates between both output transistors at a rate faster than 60hz. 5. full temperature range specifcations are guaranteed but not tested. p r o d u c t i n n o v a t i o n f r o m
pa10 ? pa10a pa10u 3 0 10k frequency, f (hz) 0 common mode rejection common mode rejection, cmr (db) 40 80 120 .1m 10 100 1k 1m 20 60 100 0 time, t (s) pulse response output voltage, v o (v) C8 2 4 6 8 10 12 C6 C4 C2 0 2 4 6 8 v in = 5v, t r = 100ns 0 20 40 60 80 100 120 temperature, t (c) 0 10 30 50 power derating internal power dissipation, p(w) 20 70 140 40 60 pa10 pa10a t = t c t = t a C50 C25 50 100 case temperature, t c (c) 0 3.0 current limit current limit, i lim (a) 2.5 0 25 75 1.0 1.5 .5 2.0 r cl = 0.6 r cl = 0.3 125 3.5 C50 0 100 .4 1.0 2.2 2.5 bias current 1.6 .7 C25 25 50 75 1.9 normalized bias current, i b (x) 125 1.3 case temperature, t c ( c) 10k 20k 50k .1m frequency, f (hz) 4.6 output voltage, v o (v pp ) power response 30k 70k 6.8 10 15 22 32 46 68 100 |+v s | + |Cv s | = 30v s s |+v s | + |Cv s | = 80v |+v s | + |Cv s | = 100v 10 100 10k .1m frequency, f (hz) input noise voltage, v n (nv/ hz) input noise 1k 10 20 30 40 50 70 100 100 1k 3k .1m frequency, f (hz) .003 .3 3 harmonic distortion distortion (%) .01 .1 1 300 10k 30k .03 a v = 10 v s = 38v r l = 8 p o = 50mw p o = 2w p o = 60w 40 100 total supply voltage, v s (v) .4 .6 1.6 quiescent current normalized quiescent current, i q (x) .8 1.4 50 60 70 80 90 1.2 1.0 t c = -25c t c = 25c t c = 85c t c = 125c 0 2 3 output current, i o (a) 2 6 output voltage swing voltage drop from supply, (v) 3 5 1 5 1 4 t c = 25c t c = 25 to 85c t c = 25c t c = 25 to 85c 4 Cv o +v o 1 100 10m frequency, f (hz) C20 0 60 120 small signal response open loop gain, a ol (db) 20 40 80 100 10 1k 10k .1m 1m 1 100 .1m 10m C140 C100 C40 0 phase response C60 C20 1k 10 10k 1m frequency, f (hz) phase, ? () C120 C80 C180 C160 p r o d u c t i n n o v a t i o n f r o m
pa10 ? pa10a 4 pa10u general please read application note 1 "general operating con - siderations" which covers stability, supplies, heat sinking, mounting, current limit, soa interpretation, and specifcation interpretation. visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; apex precision powers complete application notes library; technical seminar workbook; and evaluation kits. safe operating area (soa) the output stage of most power amplifers has three distinct limitations: 1. the current handling capability of the transistor geometry and the wire bonds. 2. the second breakdown effect which occurs whenever the simultaneous collector current and collector-emitter voltage exceeds specifed limits. 3. the junction temperature of the output transistors. the soa curves combine the effect of these limits. for a given application, the direction and magnitude of the output current should be calculated or measured and checked against the soa curves. this is simple for resistive loads but more complex for reactive and emf generating loads. 1. for dc outputs, especially those resulting from fault condi - tions, check worst case stress levels against the new soa graph. for sine wave outputs, use power design 1 to plot a load line. make sure the load line does not cross the 0.5ms limit and that excursions beyond any other second breakdown line do not exceed the time label, and have a duty cycle of no more than 10%. 1 note 1. power design is a self-extracting excel spread - sheet available free from www.cirrus.com for other waveform outputs, manual load line plotting is recommended. applications note 22, soa and load lines, will be helpful. a spice type analysis can be very useful in that a hardware setup often calls for instruments or amplifers with wide common mode rejection ranges. 2. the amplifer can handle any emf generating or reactive load and short circuits to the supply rail or shorts to com - mon if the current limits are set as follows at t c = 85c: t c = 125c thermal steady state second breakdown t = 1ms t = 5ms t = 0.5ms .2 .3 .4 .6 .8 1.0 1.5 2.0 3.0 4.0 5.0 10 15 20 25 30 35 40 50 60 70 80 100 t c = 85c supply to output differential voltage v s C v o (v) output current from +v s or C v s (a) short to v s short to v s c, l, or emf load common 50v .21a .61a 40v .3a .87a 35v .36a 1.0a 30v .46a 1.4a 25v .61a 1.7a 20v .87a 2.2a 15v 1.4a 2.9a current limiting refer to application note 9, "current limiting", for details of both fxed and foldover current limit operation. visit the apex precision power web site at www.cirrus.com for a copy of the power design spreadsheet (excel) which plots current limits vs. steady state soa. beware that current limit should be thought of as a +/C20% function initially and varies about 2:1 over the range of C55c to 125c. for fxed current limit, leave pin 7 open and use equations 1 and 2. r cl = 0.65/l cl (1) i cl = 0.65/r cl (2) where: i cl is the current limit in amperes. r cl is the current limit resistor in ohms. for certain applications, foldover current limit adds a slope to the current limit which allows more power to be delivered to the load without violating the soa. for maximum foldover slope, ground pin 7 and use equations 3 and 4. 0.65 + (vo * 0.014) i cl = (3) r cl 0.65 + (vo * 0.014) r cl = (4) i cl where: vo is the output voltage in volts. most designers start with either equation 1 to set r cl for the desired current at 0v out, or with equation 4 to set r cl at the maximum output voltage. equation 3 should then be used to plot the resulting foldover limits on the soa graph. if equa - tion 3 results in a negative current limit, foldover slope must be reduced. this can happen when the output voltage is the opposite polarity of the supply conducting the current. in applications where a reduced foldover slope is desired, this can be achieved by adding a resistor (r fo ) between pin 7 and ground. use equations 4 and 5 with this new resistor in the circuit. 0.65 + vo * 0.14 10.14 + r fo i cl = (5) r cl 0.65 + vo * 0.14 10.14 + r fo r cl = (6) i cl where: r fo is in k ohms. p r o d u c t i n n o v a t i o n f r o m
pa10 ? pa10a pa10u 5 cont acting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact apex.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex precision power, apex and the apex precision power logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. p r o d u c t i n n o v a t i o n f r o m
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